An Explicit Crosstalk Aware Delay Modelling For On-Chip RLC Interconnect for Ramp Input with Skin Effect

With the increase in frequency towards the giga hertz range, the analysis of high frequency effects like skin effect etc. are becoming extensively predominant and important for high speed VLSI design. Skin effect attenuates the high frequency components of a signal more than that of the low frequency components. Noise produced in any interconnect segment may degrade the performance of the entire system. Hence accurate noise and delay modelling for RLC lines is critical for timing and system integrity analysis. Skin effect alters the values of the resistance and also the inductance, which in turn affects the system integrity in particular and its response as a whole. Till now the skin effect has been neglected for modelling the on-chip interconnects. But at high frequencies of the order of gigahertz the skin effect becomes dominant factor and needs to be considered for accurate performance analysis. In this paper, we have proposed an accurate modelling of crosstalk voltage and delay response including skin effect for ramp input in on-chip VLSI RLC interconnect. The voltage response at the output node is analysed. From the response, the crosstalk noise and delay is estimated analytically for the on-chip RLC interconnect. This paper also addresses a novel analytical model to find the impact of skin effect on the noise and delay variation in RLC interconnect, without considering the skin effect modelling in inductance under ramp input. In the proposed work the resistance variation due to the skin effect is considered in a two wire transmission line model. The correlation between the skin effect and noise is also considered. KeywordsVLSI , RLC line, Interconnects, Crosstalk, Noise, Delay